Steady-State Time-Domain Analysis Method with Variable Time Step Integration

H. Jokinen; M. Valtonen

Steady-State Time-Domain Analysis Method with Variable Time Step Integration

H. Jokinen
, M. Valtonen

Tutkimustuotos: Artikkeli kirjassa/konferenssijulkaisussa › Conference article in proceedings › Scientific › vertaisarvioitu

3 Sitaatiot (Scopus)

Alkuperäiskieli	Englanti
Otsikko	ICECS'96, Rhodos 13-17.10.1996
Julkaisupaikka	Rhodos
Sivut	1139-1142
Tila	Julkaistu - 1996
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisussa

Tutkimusalat

APLAC
circuit simulation
steady-state analysis method

Siteeraa tätä

@inproceedings{5935a96e2e0a411eb27b5425838c3add,

title = "Steady-State Time-Domain Analysis Method with Variable Time Step Integration",

keywords = "APLAC, circuit simulation, steady-state analysis method, APLAC, circuit simulation, steady-state analysis method, APLAC, circuit simulation, steady-state analysis method",

author = "H. Jokinen and M. Valtonen",

year = "1996",

language = "English",

pages = "1139--1142",

booktitle = "ICECS'96, Rhodos 13-17.10.1996",

}

TY - GEN

T1 - Steady-State Time-Domain Analysis Method with Variable Time Step Integration

AU - Jokinen, H.

AU - Valtonen, M.

PY - 1996

Y1 - 1996

KW - APLAC

KW - circuit simulation

KW - steady-state analysis method

KW - APLAC

KW - circuit simulation

KW - steady-state analysis method

KW - APLAC

KW - circuit simulation

KW - steady-state analysis method

M3 - Conference article in proceedings

SP - 1139

EP - 1142

BT - ICECS'96, Rhodos 13-17.10.1996

CY - Rhodos

ER -