Open-loop all-digital delay line with on-chip calibration via self-equalizing delays

Tutkimustuotos: Artikkeli kirjassa/konferenssijulkaisussaConference contributionScientificvertaisarvioitu

1 Sitaatiot (Scopus)
19 Lataukset (Pure)

Abstrakti

A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the external period and reference delay is then readjusted. When on-board settling monitor observes repetition of reference delay settings, it locks delay line by applying previously collected settings. The delay line is shown to lock in presence of 30% static offset of delays from their designed values. Furthermore, random spread of delays worsened by 3 times (5% PP to 15% PP ) results in only 2% decline (3% PP to 5% PP ) after applying the proposed calibration to 16-delays line.
AlkuperäiskieliEnglanti
Otsikko23rd European Conference on Circuit Theory and Design (ECCTD 2017)
KustantajaIEEE
Sivut1-4
ISBN (elektroninen)978-1-5386-3974-0
ISBN (painettu)978-1-5386-3975-7
DOI - pysyväislinkit
TilaJulkaistu - 2017
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisuussa
TapahtumaEuropean Conference on Circuit Theory and Design - Università degli Studi di Catania - Piazza Università, 2 - 95131 Catania, Catania, Italia
Kesto: 4 syysk. 20176 syysk. 2017
Konferenssinumero: 23
http://www.ecctd2017.dieei.unict.it

Julkaisusarja

NimiEuropean Conference on Circuit Theory and Design
ISSN (elektroninen)2474-9672

Conference

ConferenceEuropean Conference on Circuit Theory and Design
LyhennettäECCTD
Maa/AlueItalia
KaupunkiCatania
Ajanjakso04/09/201706/09/2017
www-osoite

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