TY - JOUR
T1 - Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs
AU - Jarvinen, Okko
AU - Kempi, Ilia
AU - Unnikrishnan, Vishnu
AU - Stadius, Kari
AU - Kosunen, Marko
AU - Ryynänen, Jussi
PY - 2022/1/24
Y1 - 2022/1/24
N2 - This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an 8× TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.
AB - This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an 8× TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.
KW - time based
KW - time interleaving
KW - analog-to-digital converter (ADC)
KW - cyclic-coupled ring oscillator (CCRO)
KW - digital calibration
KW - finite-impulse response (FIR)
KW - least mean-square (LMS)
KW - mismatch
KW - timing skew
UR - http://www.scopus.com/inward/record.url?scp=85124103228&partnerID=8YFLogxK
U2 - 10.1109/LSSC.2022.3145918
DO - 10.1109/LSSC.2022.3145918
M3 - Article
SN - 2573-9603
VL - 5
SP - 9
EP - 12
JO - IEEE Solid-State Circuits Letters
JF - IEEE Solid-State Circuits Letters
ER -