Efficiency enhanced voltage multiplier circuit for RF energy harvesting

Shailesh Singh Chouhan*, Marko Nurmi, Kari Halonen

*Tämän työn vastaava kirjoittaja

Tutkimustuotos: LehtiartikkeliArticleScientificvertaisarvioitu

20 Sitaatiot (Scopus)

Abstrakti

In this work, a simple cascading scheme is proposed for the voltage multiplier (VM) circuit used in RF-energy harvesting. As a result, two switches are eliminated from a traditional two-stage VM circuit. In practice, the traditional two-stage VM circuit is formed by cascading of two standard differential drive rectifiers. The conventional and proposed architectures have been designed and fabricated in a standard 0.18 μm CMOS technology. The resistors of values 5 kΩ, 9 kΩ, 30 kΩ and 100 kΩ, respectively, were used to emulate practical load conditions in the measurement. The performance of the circuits was measured in terms of the power conversion efficiency (PCE), and this characterization was done for RF input power ranging from 20 dBm to 0 dBm. The measured results show that the power conversion efficiency performance at lower input RF power level has been improved in the proposed circuit as compared to the traditional VM circuit. In the best case, the proposed rectifier exhibits the measured maximum power conversion efficiency of 74% at the input RF level of 2 dBm for the resistive load of 5 kΩ.

AlkuperäiskieliEnglanti
Sivut95-102
Sivumäärä8
JulkaisuMicroelectronics Journal
Vuosikerta48
NumeroFebruary 2016
DOI - pysyväislinkit
TilaJulkaistu - 1 helmikuuta 2016
OKM-julkaisutyyppiA1 Julkaistu artikkeli, soviteltu

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