The performance of full-duplex transceivers is highly dependent on their ability to remove the self-interference (SI) that is generated by the simultaneous transmission and reception in the same frequency band. Even after passive isolation and RF cancellation, the magnitude of the residual SI is usually considerably higher than the signal of interest. The resolution of the analog-to-digital converter (ADC) must be rather high to accommodate both the residual SI and the intended signal to allow the digital SI cancellation. Adding to this technical challenge, 5G systems will occupy large signal bandwidths of hundreds of MHz. Thereby, high-speed and high resolution ADCs are required. In order to obtain a reasonable compromise between performance and massive production cost, a time-interleaved ADC (TI ADC) structure is often used. In this paper, we analyze the TI-ADC induced nonlinear distortion on the performance of a full-duplex transceiver. In particular, time-mismatch errors are considered, and in addition, we apply a digital post-processing to mitigate ADC imperfections. Simulation results show that even a slight mismatch in the TI ADC array can severely deteriorate the performance of the whole system. On the other hand, we show that included ADC compensation can restore adequate performance.