A temperature and process compensation circuit for resistive-based in-memory computing arrays

Tutkimustuotos: Artikkeli kirjassa/konferenssijulkaisussaConference article in proceedingsScientificvertaisarvioitu

4 Sitaatiot (Scopus)
61 Lataukset (Pure)

Abstrakti

In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

AlkuperäiskieliEnglanti
OtsikkoISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
KustantajaIEEE
ISBN (elektroninen)978-1-6654-5109-3
ISBN (painettu)978-1-6654-5110-9
DOI - pysyväislinkit
TilaJulkaistu - 2023
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaIEEE International Symposium on Circuits and Systems - Monterey, Yhdysvallat
Kesto: 21 toukok. 202325 toukok. 2023
Konferenssinumero: 56

Julkaisusarja

NimiIEEE International Symposium on Circuits and Systems proceedings
Vuosikerta2023-May
ISSN (painettu)0271-4310
ISSN (elektroninen)2158-1525

Conference

ConferenceIEEE International Symposium on Circuits and Systems
LyhennettäISCAS
Maa/AlueYhdysvallat
KaupunkiMonterey
Ajanjakso21/05/202325/05/2023

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