This letter presents a method for optimum selection of synchronous buck converter switch bridge topology and devices in the CMOS technology of choice. The comparative method targets maximum power efficiency, and it assumes an application where the dc-dc converter is on the same IC as the load with a known constant operating point. As its principal idea, the method circumvents the need for exhaustive comparative simulation work to cover the vast design space of available MOS device and cascode/noncascode topology combinations. Instead, the method narrows the space by using a set of basic parameters to approximate the best combination. The result, thus, provides sharp focus for subsequent detailed design and topology-dependent optimization. The method is illustrated by comparing its results to simulations of synchronous 3.3-1.65-V buck converters in 45 and 65-nm CMOS with core, I/O, and high-voltage devices.