A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

The software-defined radio paradigm calls for increasingly digital-intensive programmable receivers, ideally placing the analog-to-digital converter (ADC) right at the antenna. Such an RF ADC should be tunable over several GHz, have programmable gain, low noise, be blocker-tolerant, and consume minimal power. As an attempt to satisfy these requirements, delta-sigma (ΔΣ) modulation close to the antenna interface has been proposed in both bandpass [1], [2] and downconverting [3], [4] configurations. The latter technique enables simpler GHz-range wideband (WB) operation with low power consumption, but such receivers navigate a tradeoff between sensitivity and blocker toleration. The narrowband (NB) direct ΔΣ structure introduced in [3] combined RF N-path filtering, upconverted ΔΣ RF feedback, and a second RF gain stage to obtain acceptable noise and linearity simultaneously. In this paper we present a WB direct ΔΣ receiver, designed for programmable, inductorless operation in the long-term evolution (LTE) frequency division duplexing bands from 0.7 to 2.7GHz. The 40nm CMOS circuit uses a supply of 1.1V and provides RF channel bandwidths up to 20MHz, 37dB maximum gain, NF of 5.9 to 8.8dB, and -2dBm IIP3. A design strategy that emphasizes ΔΣ coefficient programmability ensures good performance throughout the frequency range. © 2014 IEEE.