A 60-GHz CMOS receiver with an on-chip ADC

Mikko Varonen; Mikko Kaltiokallio; Ville Saari; Olli Viitala; Mikko Kärkkäinen; Saska Lindfors; Jussi Ryynänen; Kari A I Halonen

doi:10.1109/RFIC.2009.5135577

A 60-GHz CMOS receiver with an on-chip ADC

Mikko Varonen^*, Mikko Kaltiokallio, Ville Saari, Olli Viitala, Mikko Kärkkäinen, Saska Lindfors, Jussi Ryynänen, Kari A I Halonen

^*Tämän työn vastaava kirjoittaja

Texas Instruments

Tutkimustuotos: Artikkeli kirjassa/konferenssijulkaisussa › Conference contribution › Scientific › vertaisarvioitu

20 Sitaatiot (Scopus)

Abstrakti

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

Alkuperäiskieli	Englanti
Otsikko	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Sivut	445-448
Sivumäärä	4
DOI - pysyväislinkit	https://doi.org/10.1109/RFIC.2009.5135577
Tila	Julkaistu - 2009
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisuussa
Tapahtuma	IEEE Radio Frequency Integrated Circuits Symposium - Boston, Yhdysvallat Kesto: 7 kesäk. 2009 → 9 kesäk. 2009

Conference

Conference	IEEE Radio Frequency Integrated Circuits Symposium
Lyhennettä	RFIC
Maa/Alue	Yhdysvallat
Kaupunki	Boston
Ajanjakso	07/06/2009 → 09/06/2009

Pääsy asiakirjaan

10.1109/RFIC.2009.5135577

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@inproceedings{92b4be8ae25f4601b4a8ea499bb14415,

title = "A 60-GHz CMOS receiver with an on-chip ADC",

abstract = "A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.",

keywords = "ADC, CMOS, MMIC receivers",

author = "Mikko Varonen and Mikko Kaltiokallio and Ville Saari and Olli Viitala and Mikko K{\"a}rkk{\"a}inen and Saska Lindfors and Jussi Ryyn{\"a}nen and Halonen, {Kari A I}",

year = "2009",

doi = "10.1109/RFIC.2009.5135577",

language = "English",

isbn = "9781424433780",

pages = "445--448",

booktitle = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

note = "IEEE Radio Frequency Integrated Circuits Symposium, RFIC ; Conference date: 07-06-2009 Through 09-06-2009",

}

Varonen, M, Kaltiokallio, M, Saari, V, Viitala, O, Kärkkäinen, M, Lindfors, S, Ryynänen, J & Halonen, KAI 2009, A 60-GHz CMOS receiver with an on-chip ADC. julkaisussa Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium., 5135577, Sivut 445-448, IEEE Radio Frequency Integrated Circuits Symposium, Boston, Massachusetts, Yhdysvallat, 07/06/2009. https://doi.org/10.1109/RFIC.2009.5135577

TY - GEN

T1 - A 60-GHz CMOS receiver with an on-chip ADC

AU - Varonen, Mikko

AU - Kaltiokallio, Mikko

AU - Saari, Ville

AU - Viitala, Olli

AU - Kärkkäinen, Mikko

AU - Lindfors, Saska

AU - Ryynänen, Jussi

AU - Halonen, Kari A I

PY - 2009

Y1 - 2009

N2 - A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

AB - A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

KW - ADC

KW - CMOS

KW - MMIC receivers

UR - http://www.scopus.com/inward/record.url?scp=70350230270&partnerID=8YFLogxK

U2 - 10.1109/RFIC.2009.5135577

DO - 10.1109/RFIC.2009.5135577

M3 - Conference contribution

AN - SCOPUS:70350230270

SN - 9781424433780

SP - 445

EP - 448

BT - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

T2 - IEEE Radio Frequency Integrated Circuits Symposium

Y2 - 7 June 2009 through 9 June 2009

ER -

A 60-GHz CMOS receiver with an on-chip ADC

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Conference

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