A 3.5-GHz Digitally-Controlled Open-Loop Fractional-N Frequency Divider in 28-nm CMOS

Tze Hin Cheung, Mikko Martelius, Yury Antonov, Rehman Akbar, Jussi Ryynänen, Aarno Pärssinen, Kari Stadius

Tutkimustuotos: Artikkeli kirjassa/konferenssijulkaisussaConference contributionScientificvertaisarvioitu


This paper describes the design and measurement of an open-loop fractional frequency divider implementation. The fractional divider consists of a multi-modulus integer frequency divider (MMD), a sigma-delta modulator (SDM) and a pipelined phase interpolator. The fractional frequency division is achieved with the MMD and the 13-bit SDM toggling the integer division ratio. The resulting signal is then processed by the phase interpolator which significantly reduces the spurs by 22 dB and generates spectrally clean signal with correct output frequency. The prototype is implemented in 28-nm CMOS technology and it operates within input frequency range of 1.9 GHz - 3.5 GHz with fractional division ratio in between 2-3. As an example of the operation, with a setting of an arbitrary division ratio of 2.3164 and input frequency of 2.4 GHz, the output sets correctly to 1.0361 GHz with RMS jitter of 2.1 ps.
Otsikko2020 IEEE International Symposium on Circuits and Systems (ISCAS)
ISBN (elektroninen)978-1-7281-3320-1
ISBN (painettu)978-1-7281-3321-8
DOI - pysyväislinkit
TilaJulkaistu - 2021
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisuussa
TapahtumaIEEE International Symposium on Circuits and Systems - Seville, Espanja
Kesto: 10 lokakuuta 202021 lokakuuta 2020


NimiIEEE International Symposium on Circuits and Systems proceedings
ISSN (painettu)0271-4302
ISSN (elektroninen)2158-1525


ConferenceIEEE International Symposium on Circuits and Systems

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