Abstrakti
The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.
Alkuperäiskieli | Englanti |
---|---|
Otsikko | Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 |
Kustantaja | IEEE |
ISBN (elektroninen) | 9781479932863 |
DOI - pysyväislinkit | |
Tila | Julkaistu - 4 marrask. 2014 |
OKM-julkaisutyyppi | A4 Artikkeli konferenssijulkaisussa |
Tapahtuma | IEEE Custom Integrated Circuits Conference: The Showcase for Integrated Circuit Design in the Heart of Silicon Valley - San Jose, Yhdysvallat Kesto: 15 syysk. 2014 → 17 syysk. 2014 Konferenssinumero: 36 |
Conference
Conference | IEEE Custom Integrated Circuits Conference |
---|---|
Lyhennettä | CiCC |
Maa/Alue | Yhdysvallat |
Kaupunki | San Jose |
Ajanjakso | 15/09/2014 → 17/09/2014 |