A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

Miikka Tenhunen; Kalle Spoof; Vishnu Unnikrishnan; Kari Stadius; Marko Kosunen; Jussi Ryynanen

doi:10.1109/NEWCAS52662.2022.9841992

A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

Miikka Tenhunen^*, Kalle Spoof, Vishnu Unnikrishnan, Kari Stadius, Marko Kosunen, Jussi Ryynanen

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Tutkimustuotos: Artikkeli kirjassa/konferenssijulkaisussa › Conference contribution › Scientific › vertaisarvioitu

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4 Lataukset (Pure)

Abstrakti

This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

Alkuperäiskieli	Englanti
Otsikko	20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings
Kustantaja	IEEE
Sivut	35-39
Sivumäärä	5
ISBN (elektroninen)	978-1-6654-0105-0
DOI - pysyväislinkit	https://doi.org/10.1109/NEWCAS52662.2022.9841992
Tila	Julkaistu - 2022
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisuussa
Tapahtuma	IEEE International New Circuits and Systems Conference - Quebec City, Kanada Kesto: 19 kesäk. 2022 → 22 kesäk. 2022 Konferenssinumero: 20

Conference

Conference	IEEE International New Circuits and Systems Conference
Lyhennettä	NEWCAS
Maa/Alue	Kanada
Kaupunki	Quebec City
Ajanjakso	19/06/2022 → 22/06/2022

Pääsy asiakirjaan

10.1109/NEWCAS52662.2022.9841992

Tenhunen_et_al_A2Gs_time_interleavedAccepted author manuscript, 737 KB

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@inproceedings{6d0912cb2a754f4f9397decd8681f366,

title = "A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps",

abstract = "This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step. ",

keywords = "high-speed ADC, SAR ADC, time-interleaved ADC",

author = "Miikka Tenhunen and Kalle Spoof and Vishnu Unnikrishnan and Kari Stadius and Marko Kosunen and Jussi Ryynanen",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; IEEE International New Circuits and Systems Conference, NEWCAS ; Conference date: 19-06-2022 Through 22-06-2022",

year = "2022",

doi = "10.1109/NEWCAS52662.2022.9841992",

language = "English",

pages = "35--39",

booktitle = "20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings",

publisher = "IEEE",

address = "United States",

}

Tenhunen, M, Spoof, K, Unnikrishnan, V, Stadius, K , Kosunen, M & Ryynanen, J 2022, A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps. julkaisussa 20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings. IEEE, Sivut 35-39, IEEE International New Circuits and Systems Conference, Quebec City, Kanada, 19/06/2022. https://doi.org/10.1109/NEWCAS52662.2022.9841992

TY - GEN

T1 - A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

AU - Tenhunen, Miikka

AU - Spoof, Kalle

AU - Unnikrishnan, Vishnu

AU - Stadius, Kari

AU - Kosunen, Marko

AU - Ryynanen, Jussi

N1 - Conference code: 20

PY - 2022

Y1 - 2022

N2 - This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

AB - This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

KW - high-speed ADC

KW - SAR ADC

KW - time-interleaved ADC

UR - http://www.scopus.com/inward/record.url?scp=85138706714&partnerID=8YFLogxK

U2 - 10.1109/NEWCAS52662.2022.9841992

DO - 10.1109/NEWCAS52662.2022.9841992

M3 - Conference contribution

AN - SCOPUS:85138706714

SP - 35

EP - 39

BT - 20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings

PB - IEEE

T2 - IEEE International New Circuits and Systems Conference

Y2 - 19 June 2022 through 22 June 2022

ER -

A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

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