Voltage to time converter comprises a differential input (201) with a first node (301) and a second node (302), for receiving an input voltage in the form of a potential difference between said first and second nodes (301, 302). A clock input (202) is provided for receiving a clock signal (CK), and a sample and hold circuit (203) is coupled to said differential input (201) for temporarily storing a sample of said input voltage according to a sampling schedule defined by said clock signal (CK). A level shifter (204) is coupled to said sample and hold circuit (203) for controllably shifting a level of the stored sample to produce a level-shifted sample. A ramp generator (205) generates a ramp voltage according to a conversion schedule defined by said clock signal (CK). A comparator (206) is configured to compare the generated ramp voltage to a threshold and to output a stop signal (STOP) in response to said ramp voltage reaching said threshold. Said ramp generator (205) is configured to use said level-shifted sample as an offset in generating said ramp voltage.
|IPC||H03M 1/ 56 A I|
|Publication status||Published - 26 Nov 2020|
|MoE publication type||H1 Granted patent|