Voltage multiplier arrangement for heavy load conditions in RF energy harvesting

Shailesh Singh Chouhan*, Kari Halonen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

1 Citation (Scopus)

Abstract

In this work, a two-stage voltage multiplier (VM) is proposed where, an additional DC bias voltage has been derived directly from the input RF signal. As a result, the load driving capability of the proposed rectifier is higher for the heavy load conditions. The heavy load condition stands for the value of the load resistor lower than 30K Omega. The proposed architecture has been designed and fabricated in a standard 0.18 mu m CMOS technology. The measurements were done by emulating real load condition in terms of the resistance of values 1K Omega, 5K Omega, 10K Omega, 30K Omega and 100K Omega (light load). The measured power conversion efficiency (PCE) at ISM 433 MHz frequency is 43.4 % at -8 dBm for the resistive load of 5K Omega.

Original languageEnglish
Title of host publication2016 IEEE Nordic Circuits and Systems Conference (NORCAS)
PublisherIEEE
Number of pages5
ISBN (Electronic)978-1-5090-1095-0
DOIs
Publication statusPublished - 2016
MoE publication typeA4 Article in a conference publication
EventIEEE Nordic Circuits and Systems Conference - Copenhagen, Denmark
Duration: 1 Nov 20162 Nov 2016
Conference number: 2

Conference

ConferenceIEEE Nordic Circuits and Systems Conference
Abbreviated title NORCAS
CountryDenmark
CityCopenhagen
Period01/11/201602/11/2016

Keywords

  • CMOS RECTIFIER
  • DESIGN

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