Variable Threshold (MOS) - Transistor for Integrated Neural Network Circuits

A. Rantala; S. Franssila; K. Kaski; J. Lampinen; M. Åberg

Variable Threshold (MOS) - Transistor for Integrated Neural Network Circuits

A. Rantala, S. Franssila, K. Kaski, J. Lampinen, M. Åberg

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Original language	English
Title of host publication	NORCHIP´97, Tanska
Pages	36-43
Publication status	Published - 1997
MoE publication type	A4 Conference publication

Keywords

integrated neural network circuits
variable threshold MOS

Cite this

@inproceedings{dff7b0a8850d4e77ba5cd3eef5bdcae7,

title = "Variable Threshold (MOS) - Transistor for Integrated Neural Network Circuits",

keywords = "integrated neural network circuits, variable threshold MOS, integrated neural network circuits, variable threshold MOS, integrated neural network circuits, variable threshold MOS",

author = "A. Rantala and S. Franssila and K. Kaski and J. Lampinen and M. {\AA}berg",

year = "1997",

language = "English",

pages = "36--43",

booktitle = "NORCHIP´97, Tanska",

}

TY - GEN

T1 - Variable Threshold (MOS) - Transistor for Integrated Neural Network Circuits

AU - Rantala, A.

AU - Franssila, S.

AU - Kaski, K.

AU - Lampinen, J.

AU - Åberg, M.

PY - 1997

Y1 - 1997

KW - integrated neural network circuits

KW - variable threshold MOS

KW - integrated neural network circuits

KW - variable threshold MOS

KW - integrated neural network circuits

KW - variable threshold MOS

M3 - Conference article in proceedings

SP - 36

EP - 43

BT - NORCHIP´97, Tanska

ER -