Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Jani Makipaa, Arto Rantala, Matti Sopanen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)


    To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

    Original languageEnglish
    Title of host publication2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
    ISBN (Electronic)978-1-4799-7439-9
    Publication statusPublished - 30 Jan 2014
    MoE publication typeA4 Article in a conference publication
    EventIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - Millbrae, United States
    Duration: 6 Oct 20149 Oct 2014


    ConferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    Abbreviated titleS3S
    CountryUnited States
    Internet address

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