To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.
|Title of host publication||2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014|
|Publication status||Published - 30 Jan 2014|
|MoE publication type||A4 Article in a conference publication|
|Event||IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - Millbrae, United States|
Duration: 6 Oct 2014 → 9 Oct 2014
|Conference||IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference|
|Period||06/10/2014 → 09/10/2014|