Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking

Tommi Junttila; Ilkka Niemelä

doi:10.1007/3-540-44957-4_37

Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

32 Citations (Scopus)

Original language	English
Title of host publication	1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings
Subtitle of host publication	Putting Theory into Practice
Editors	J. Lloyd, V. Dahl, U. Furbach, M. Kerber, K. Lau, C. Palamidessi, L. Pereira, Y. Sagiv, P. Stuckey
Place of Publication	Berlin, Germany
Publisher	Springer
Pages	553-567
ISBN (Electronic)	978-3-540-44957-7
ISBN (Print)	978-3-540-67797-0
DOIs	https://doi.org/10.1007/3-540-44957-4_37
Publication status	Published - 2000
MoE publication type	A4 Conference publication

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer Berlin Heidelberg
Volume	1861
ISSN (Print)	0302-9743

Keywords

Boolean circuits
satisfiability checking

Access to Document

10.1007/3-540-44957-4_37

Cite this

Junttila, T., & Niemelä, I. (2000). Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking. In J. Lloyd, V. Dahl, U. Furbach, M. Kerber, K. Lau, C. Palamidessi, L. Pereira, Y. Sagiv, & P. Stuckey (Eds.), 1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings: Putting Theory into Practice (pp. 553-567). (Lecture Notes in Computer Science ; Vol. 1861). Springer. https://doi.org/10.1007/3-540-44957-4_37

Junttila, Tommi ; Niemelä, Ilkka. / Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking. 1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings: Putting Theory into Practice. editor / J. Lloyd ; V. Dahl ; U. Furbach ; M. Kerber ; K. Lau ; C. Palamidessi ; L. Pereira ; Y. Sagiv ; P. Stuckey. Berlin, Germany : Springer, 2000. pp. 553-567 (Lecture Notes in Computer Science ).

@inproceedings{48772b1671dc4b5aa870a1e2be962e27,

title = "Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking",

keywords = "Boolean circuits, satisfiability checking, Boolean circuits, satisfiability checking, Boolean circuits, satisfiability checking",

author = "Tommi Junttila and Ilkka Niemel{\"a}",

year = "2000",

doi = "10.1007/3-540-44957-4_37",

language = "English",

isbn = "978-3-540-67797-0",

series = "Lecture Notes in Computer Science ",

publisher = "Springer",

pages = "553--567",

editor = "J. Lloyd and V. Dahl and U. Furbach and M. Kerber and K. Lau and C. Palamidessi and L. Pereira and Y. Sagiv and P. Stuckey",

booktitle = "1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings",

address = "Germany",

}

Junttila, T & Niemelä, I 2000, Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking. in J Lloyd, V Dahl, U Furbach, M Kerber, K Lau, C Palamidessi, L Pereira, Y Sagiv & P Stuckey (eds), 1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings: Putting Theory into Practice. Lecture Notes in Computer Science , vol. 1861, Springer, Berlin, Germany, pp. 553-567. https://doi.org/10.1007/3-540-44957-4_37

Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking. / Junttila, Tommi ; Niemelä, Ilkka.
1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings: Putting Theory into Practice. ed. / J. Lloyd; V. Dahl; U. Furbach; M. Kerber; K. Lau; C. Palamidessi; L. Pereira; Y. Sagiv; P. Stuckey. Berlin, Germany: Springer, 2000. p. 553-567 (Lecture Notes in Computer Science ; Vol. 1861).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking

AU - Junttila, Tommi

AU - Niemelä, Ilkka

PY - 2000

Y1 - 2000

KW - Boolean circuits

KW - satisfiability checking

KW - Boolean circuits

KW - satisfiability checking

KW - Boolean circuits

KW - satisfiability checking

U2 - 10.1007/3-540-44957-4_37

DO - 10.1007/3-540-44957-4_37

M3 - Conference article in proceedings

SN - 978-3-540-67797-0

T3 - Lecture Notes in Computer Science

SP - 553

EP - 567

BT - 1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings

A2 - Lloyd, J.

A2 - Dahl, V.

A2 - Furbach, U.

A2 - Kerber, M.

A2 - Lau, K.

A2 - Palamidessi, C.

A2 - Pereira, L.

A2 - Sagiv, Y.

A2 - Stuckey, P.

PB - Springer

CY - Berlin, Germany

ER -

Junttila T , Niemelä I. Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking. In Lloyd J, Dahl V, Furbach U, Kerber M, Lau K, Palamidessi C, Pereira L, Sagiv Y, Stuckey P, editors, 1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings: Putting Theory into Practice. Berlin, Germany: Springer. 2000. p. 553-567. (Lecture Notes in Computer Science ). doi: 10.1007/3-540-44957-4_37