Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    27 Citations (Scopus)
    Original languageEnglish
    Title of host publication1st International Conference on Computational Logic, CL 2000, London, UK, July 24–28, 2000. Proceedings
    Subtitle of host publicationPutting Theory into Practice
    EditorsJ. Lloyd, V. Dahl, U. Furbach, M. Kerber, K. Lau, C. Palamidessi, L. Pereira, Y. Sagiv, P. Stuckey
    Place of PublicationBerlin, Germany
    Pages553-567
    ISBN (Electronic)978-3-540-44957-7
    DOIs
    Publication statusPublished - 2000
    MoE publication typeA4 Article in a conference publication

    Publication series

    NameLecture Notes in Computer Science
    PublisherSpringer Berlin Heidelberg
    Volume1861
    ISSN (Print)0302-9743

    Keywords

    • Boolean circuits
    • satisfiability checking

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