Systolic Array for Binary Multiplier

Ling Wang, I. Hartimo

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Original language	English
Title of host publication	Int. Symposium on Speech, Image & Neural Networks, Hong Kong, April 13-16, 1994
Editors	IEEE Hong Kong Chapter of Signal Processing
Place of Publication	Hong Kong
Pages	745-748
Publication status	Published - 1994
MoE publication type	A4 Conference publication

Keywords

@inproceedings{f53d8c7680ba42a0914c6a092754a0c7,

title = "Systolic Array for Binary Multiplier",

keywords = "binary multiplier, systolic architecture, binary multiplier, systolic architecture, binary multiplier, systolic architecture",

author = "Ling Wang and I. Hartimo",

year = "1994",

language = "English",

pages = "745--748",

editor = "{Hong Kong Chapter of Signal Processing}, IEEE",

booktitle = "Int. Symposium on Speech, Image & Neural Networks, Hong Kong, April 13-16, 1994",

}

TY - GEN

T1 - Systolic Array for Binary Multiplier

AU - Wang, Ling

AU - Hartimo, I.

PY - 1994

Y1 - 1994

KW - binary multiplier

KW - systolic architecture

KW - binary multiplier

KW - systolic architecture

KW - binary multiplier

KW - systolic architecture

M3 - Conference article in proceedings

SP - 745

EP - 748

BT - Int. Symposium on Speech, Image & Neural Networks, Hong Kong, April 13-16, 1994

A2 - Hong Kong Chapter of Signal Processing, IEEE

CY - Hong Kong

ER -