Synthesis-Aided Reliability Assurance of Basic Block Models for Model Checking Purposes

Igor Buzhinsky, Antti Pakonen, Valeriy Vyatkin

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

2 Citations (Scopus)
134 Downloads (Pure)


In the Finnish nuclear industry, model checking, a formal verification technique, is used as an additional means of safety assurance for instrumentation and control (IC) system design. Since the code of vendor-specific basic function blocks used in IC is commonly closed, these blocks need to be modeled manually based on available specification. This modeling introduces an additional source of human factor into the verification process. To increase the reliability of the library of basic blocks used in nuclear IC verification, we apply formal synthesis techniques, which can construct finite-state models of reactive systems from behavior examples and temporal properties. Since these techniques have computational limitations and synthesized models are hard to understand even by an analyst, we do not use them in the final verification process. Instead, in an iterative process, behavioral differences between a synthesized model and a manual model implementation are identified and used to create a list of features of manual implementations which either violate the specification or show that the specification is ambiguous.

Original languageEnglish
Title of host publicationProceedings of the 2018 IEEE 27th International Symposium on Industrial Electronics, ISIE 2018
Number of pages6
ISBN (Print)9781538637050
Publication statusPublished - 10 Aug 2018
MoE publication typeA4 Article in a conference publication
EventInternational Symposium on Industrial Electronics - Cairns, Australia
Duration: 13 Jun 201815 Jun 2018
Conference number: 27

Publication series

NameProceedings of the IEEE International Symposium on Industrial Electronics
ISSN (Print)2163-5137
ISSN (Electronic)2380-1395


ConferenceInternational Symposium on Industrial Electronics
Abbreviated titleISIE


  • formal synthesis
  • formal verification
  • model checking
  • nuclear IC systems


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