Steady-State Time-Domain Analysis Method with Variable Time Step Integration

H. Jokinen, M. Valtonen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)
    Original languageEnglish
    Title of host publicationICECS'96, Rhodos 13-17.10.1996
    Place of PublicationRhodos
    Pages1139-1142
    Publication statusPublished - 1996
    MoE publication typeA4 Article in a conference publication

    Keywords

    • APLAC
    • circuit simulation
    • steady-state analysis method

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