RISC-V Core with AES-256 Accelerator

Otto Simola; Aleksi Korsman; Verneri Hirvonen; Antti Tarkka; Julius Helander; Kimmo Jarvinen; Marko Kosunen; Jussi Ryynanen

doi:10.1109/ICECS61496.2024.10848921

RISC-V Core with AES-256 Accelerator

Otto Simola^*, Aleksi Korsman^*, Verneri Hirvonen^*, Antti Tarkka^*, Julius Helander^*, Kimmo Jarvinen, Marko Kosunen^*, Jussi Ryynanen^*

^*Corresponding author for this work

Xiphera Oy

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

This paper presents a RISC-V core integrated with a cryptographic accelerator for 256-bit Advanced Encryption Standard (AES-256). It supports several block cipher modes and has been integrated as an extension to a 5-stage RV32IMFC RISC-V core implemented in 22 nm FD-SOI. For performance comparison, the hardware accelerator was verified with an extensive verification environment involving simulations and testing with Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations against a C-program solution implemented with the openSSL library, running on the implemented RISC-V core. The accelerator achieves 82-84% faster AES cipher operation compared to the software solution.

Original language	English
Title of host publication	2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024
Publisher	IEEE
Number of pages	4
ISBN (Print)	979-8-3503-7721-7
DOIs	https://doi.org/10.1109/ICECS61496.2024.10848921
Publication status	Published - 2024
MoE publication type	A4 Conference publication
Event	IEEE International Conference on Electronics, Circuits and Systems - Nancy, France Duration: 18 Nov 2024 → 20 Nov 2024 Conference number: 31

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
ISSN (Print)	2994-5755
ISSN (Electronic)	2995-0589

Conference

Conference	IEEE International Conference on Electronics, Circuits and Systems
Abbreviated title	ICECS
Country/Territory	France
City	Nancy
Period	18/11/2024 → 20/11/2024

Keywords

Accelerator
AES-256
ASIC
FPGA
RISC-V

Access to Document

10.1109/ICECS61496.2024.10848921

Cite this

Simola, O., Korsman, A., Hirvonen, V., Tarkka, A., Helander, J., Jarvinen, K., Kosunen, M., & Ryynanen, J. (2024). RISC-V Core with AES-256 Accelerator. In 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). IEEE. https://doi.org/10.1109/ICECS61496.2024.10848921

@inproceedings{9e3901b27efa44f7aa1d6495052ed397,

title = "RISC-V Core with AES-256 Accelerator",

abstract = "This paper presents a RISC-V core integrated with a cryptographic accelerator for 256-bit Advanced Encryption Standard (AES-256). It supports several block cipher modes and has been integrated as an extension to a 5-stage RV32IMFC RISC-V core implemented in 22 nm FD-SOI. For performance comparison, the hardware accelerator was verified with an extensive verification environment involving simulations and testing with Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations against a C-program solution implemented with the openSSL library, running on the implemented RISC-V core. The accelerator achieves 82-84% faster AES cipher operation compared to the software solution.",

keywords = "Accelerator, AES-256, ASIC, FPGA, RISC-V",

author = "Otto Simola and Aleksi Korsman and Verneri Hirvonen and Antti Tarkka and Julius Helander and Kimmo Jarvinen and Marko Kosunen and Jussi Ryynanen",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; IEEE International Conference on Electronics, Circuits and Systems, ICECS ; Conference date: 18-11-2024 Through 20-11-2024",

year = "2024",

doi = "10.1109/ICECS61496.2024.10848921",

language = "English",

isbn = "979-8-3503-7721-7",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "IEEE",

booktitle = "2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024",

address = "United States",

}

Simola, O, Korsman, A, Hirvonen, V, Tarkka, A, Helander, J, Jarvinen, K, Kosunen, M & Ryynanen, J 2024, RISC-V Core with AES-256 Accelerator. in 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, IEEE, IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18/11/2024. https://doi.org/10.1109/ICECS61496.2024.10848921

RISC-V Core with AES-256 Accelerator. / Simola, Otto; Korsman, Aleksi; Hirvonen, Verneri et al.
2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024. IEEE, 2024. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - RISC-V Core with AES-256 Accelerator

AU - Simola, Otto

AU - Korsman, Aleksi

AU - Hirvonen, Verneri

AU - Tarkka, Antti

AU - Helander, Julius

AU - Jarvinen, Kimmo

AU - Kosunen, Marko

AU - Ryynanen, Jussi

N1 - Conference code: 31

PY - 2024

Y1 - 2024

N2 - This paper presents a RISC-V core integrated with a cryptographic accelerator for 256-bit Advanced Encryption Standard (AES-256). It supports several block cipher modes and has been integrated as an extension to a 5-stage RV32IMFC RISC-V core implemented in 22 nm FD-SOI. For performance comparison, the hardware accelerator was verified with an extensive verification environment involving simulations and testing with Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations against a C-program solution implemented with the openSSL library, running on the implemented RISC-V core. The accelerator achieves 82-84% faster AES cipher operation compared to the software solution.

AB - This paper presents a RISC-V core integrated with a cryptographic accelerator for 256-bit Advanced Encryption Standard (AES-256). It supports several block cipher modes and has been integrated as an extension to a 5-stage RV32IMFC RISC-V core implemented in 22 nm FD-SOI. For performance comparison, the hardware accelerator was verified with an extensive verification environment involving simulations and testing with Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations against a C-program solution implemented with the openSSL library, running on the implemented RISC-V core. The accelerator achieves 82-84% faster AES cipher operation compared to the software solution.

KW - Accelerator

KW - AES-256

KW - ASIC

KW - FPGA

KW - RISC-V

UR - http://www.scopus.com/inward/record.url?scp=85217620235&partnerID=8YFLogxK

U2 - 10.1109/ICECS61496.2024.10848921

DO - 10.1109/ICECS61496.2024.10848921

M3 - Conference article in proceedings

AN - SCOPUS:85217620235

SN - 979-8-3503-7721-7

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

BT - 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024

PB - IEEE

T2 - IEEE International Conference on Electronics, Circuits and Systems

Y2 - 18 November 2024 through 20 November 2024

ER -

RISC-V Core with AES-256 Accelerator

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Aalto Electronics-ICT

Cite this

RISC-V Core with AES-256 Accelerator

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Equipment

Aalto Electronics-ICT

Cite this