The integration of electronics has been an ongoing process for a few decades. Ultimately, the goal is to include all of the needed electronics in a single integrated circuit (IC), also referred to as system on chip (SoC). The evolution towards SoC is driven by the multi-billion dollar industry around smartphones. New functionalities are added while the space reserved for electronics stays constant, or in the worst case, reduces. The circuits needed for communication are at the center point of this evolution, and with a good reason. A growing list of communication standards need to be supported, while guaranteeing backward compatibility to older standards. This results in multiple parallel radio hardware chains. Ideally, these chains would be replaced by a cognitive software defined radio (SDR), that is to say, a software reconfigurable radio that is able to adapt its operation in real-time based on the current spectrum usage. To accomplish this, the transmitter and receiver have to be highly programmable, which requires digital intensive implementations. Ultimately, the transmitter and receiver are comprised only of a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC), in which case they can be referred to as digital-to-RF or RF-to-digital converters, respectively. The RF-to-digital converters are an intriguing approach to realize a cognitive SDR. Having an immediate analog-to-digital conversion after the antenna shifts the bulk of the signal processing to digital domain, which enables superior scalability and programmability over analog implementations. One promising RF-to-digital converter architecture is the direct delta-sigma receiver (DDSR), which combines a direct downconversion receiver and delta-sigma ADC. The DDSR embeds the receiver functional blocks into the delta-sigma loop-filter, and thus the digitalization of the analog input signal begins right after the antenna. The analog stages are used to their maximum potential as each stage participates in amplification, filtering and quantization noise shaping simultaneously, resulting in a compact design. The main challenge of the DDSR is that the RF frontend and the delta-sigma ADC can no longer be designed separately. Due to the increased design complexity, simple yet accurate models and design techniques are required to fully benefit from the DDSR. The objectives of this thesis are to 1) evaluate the feasibility of the DDSR as a future solution for integrated receiver, 2) provide a new perspective and understanding on the design of RF-to-digital converters, and 3) develop versatile models and design strategies that overcome the complexity of the DDSR.
|Translated title of the contribution||RF-digitaali -muuntimet: Suora delta-sigma vastaanotin|
|Publication status||Published - 2018|
|MoE publication type||G5 Doctoral dissertation (article)|