Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters

Agnimesh Ghosh; Andrei Spelman; Tze Hin Cheung; Dhanashree Boopathy; Vishnu Unnikrishnan; Vesa Lampu; Guixian Xu; Lauri Anttila; Kari Stadius; Marko Kosunen; Jussi Ryynänen

doi:10.1109/NorCAS57515.2022.9934696

Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters

Agnimesh Ghosh
, Andrei Spelman
, Tze Hin Cheung
, Dhanashree Boopathy
, Vishnu Unnikrishnan
, Vesa Lampu
, Guixian Xu
, Lauri Anttila
, Kari Stadius
, Marko Kosunen
, Jussi Ryynänen

Tampere University

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

6 Citations (Scopus)

226 Downloads (Pure)

Abstract

To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.

Original language	English
Title of host publication	2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings
Editors	Jari Nurmi, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard
Publisher	IEEE
Pages	1-7
Number of pages	7
ISBN (Electronic)	979-8-3503-4550-6
ISBN (Print)	979-8-3503-4551-3
DOIs	https://doi.org/10.1109/NorCAS57515.2022.9934696
Publication status	Published - 26 Oct 2022
MoE publication type	A4 Conference publication
Event	IEEE Nordic Circuits and Systems Conference - Oslo, Norway Duration: 25 Oct 2022 → 26 Oct 2022

Conference

Conference	IEEE Nordic Circuits and Systems Conference
Abbreviated title	NorCAS
Country/Territory	Norway
City	Oslo
Period	25/10/2022 → 26/10/2022

Keywords

digital signal processing (DSP)
5G
Reconfigurable hardware
Digital Front-end
System on Chip
Outphasing
Transmitter

Access to Document

10.1109/NorCAS57515.2022.9934696

DSP_IEEE_NorCAS_2022Accepted author manuscript, 1.46 MB

Cite this

Ghosh, A., Spelman, A., Cheung, T. H., Boopathy, D., Unnikrishnan, V., Lampu, V., Xu, G., Anttila, L., Stadius, K., Kosunen, M., & Ryynänen, J. (2022). Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters. In J. Nurmi, D. T. Wisland, S. Aunet, & K. Kjelgaard (Eds.), 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings (pp. 1-7). Article 9934696 IEEE. https://doi.org/10.1109/NorCAS57515.2022.9934696

@inproceedings{d4be4e9581714a369e886378f398cf26,

title = "Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters",

abstract = "To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61\% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.",

keywords = "digital signal processing (DSP), 5G, Reconfigurable hardware, Digital Front-end, System on Chip, Outphasing, Transmitter",

author = "Agnimesh Ghosh and Andrei Spelman and Cheung, \{Tze Hin\} and Dhanashree Boopathy and Vishnu Unnikrishnan and Vesa Lampu and Guixian Xu and Lauri Anttila and Kari Stadius and Marko Kosunen and Jussi Ryyn{\"a}nen",

year = "2022",

month = oct,

day = "26",

doi = "10.1109/NorCAS57515.2022.9934696",

language = "English",

isbn = "979-8-3503-4551-3",

pages = "1--7",

editor = "Jari Nurmi and Wisland, \{Dag T.\} and Snorre Aunet and Kristian Kjelgaard",

booktitle = "2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings",

publisher = "IEEE",

address = "United States",

note = "IEEE Nordic Circuits and Systems Conference, NorCAS ; Conference date: 25-10-2022 Through 26-10-2022",

}

Ghosh, A, Spelman, A, Cheung, TH , Boopathy, D, Unnikrishnan, V, Lampu, V, Xu, G, Anttila, L, Stadius, K , Kosunen, M & Ryynänen, J 2022, Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters. in J Nurmi, DT Wisland, S Aunet & K Kjelgaard (eds), 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings., 9934696, IEEE, pp. 1-7, IEEE Nordic Circuits and Systems Conference, Oslo, Norway, 25/10/2022. https://doi.org/10.1109/NorCAS57515.2022.9934696

Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters. / Ghosh, Agnimesh; Spelman, Andrei; Cheung, Tze Hin et al.
2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings. ed. / Jari Nurmi; Dag T. Wisland; Snorre Aunet; Kristian Kjelgaard. IEEE, 2022. p. 1-7 9934696.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters

AU - Ghosh, Agnimesh

AU - Spelman, Andrei

AU - Cheung, Tze Hin

AU - Boopathy, Dhanashree

AU - Unnikrishnan, Vishnu

AU - Lampu, Vesa

AU - Xu, Guixian

AU - Anttila, Lauri

AU - Stadius, Kari

AU - Kosunen, Marko

AU - Ryynänen, Jussi

PY - 2022/10/26

Y1 - 2022/10/26

N2 - To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.

AB - To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.

KW - digital signal processing (DSP)

KW - 5G

KW - Reconfigurable hardware

KW - Digital Front-end

KW - System on Chip

KW - Outphasing

KW - Transmitter

UR - https://www.scopus.com/pages/publications/85142432958

U2 - 10.1109/NorCAS57515.2022.9934696

DO - 10.1109/NorCAS57515.2022.9934696

M3 - Conference article in proceedings

SN - 979-8-3503-4551-3

SP - 1

EP - 7

BT - 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings

A2 - Nurmi, Jari

A2 - Wisland, Dag T.

A2 - Aunet, Snorre

A2 - Kjelgaard, Kristian

PB - IEEE

T2 - IEEE Nordic Circuits and Systems Conference

Y2 - 25 October 2022 through 26 October 2022

ER -

Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters

Abstract

Conference

Keywords

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SMArT: Switch-Mode Analog Signal Processing for Integrated 5G Transceivers

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Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Projects

SMArT: Switch-Mode Analog Signal Processing for Integrated 5G Transceivers

Cite this