Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters

Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Kari Stadius, Manil Dev Gomony, Mikko Valkama, Jussi Ryynänen, Marko Kosunen, Vishnu Unnikrishnan

Research output: Contribution to journalArticleScientificpeer-review

1 Citation (Scopus)
27 Downloads (Pure)


The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to -48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

Original languageEnglish
Article number10313121
Pages (from-to)4-15
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
Early online date8 Nov 2023
Publication statusPublished - 1 Jan 2024
MoE publication typeA1 Journal article-refereed


  • Hardware
  • Radio transmitters
  • Generators
  • 5G mobile communication
  • Signal processing
  • Modulation
  • Phase modulation


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