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To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.
|Title of host publication||2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings|
|Editors||Jari Nurmi, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard|
|Number of pages||7|
|Publication status||Published - 26 Oct 2022|
|MoE publication type||A4 Article in a conference publication|
|Event||IEEE Nordic Circuits and Systems Conference - Oslo, Norway|
Duration: 25 Oct 2022 → 26 Oct 2022
|Conference||IEEE Nordic Circuits and Systems Conference|
|Period||25/10/2022 → 26/10/2022|
- digital signal processing (DSP)
- Reconfigurable hardware
- Digital Front-end
- System on Chip
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- 1 Active
SMArT: Switch-Mode Analog Signal Processing for Integrated 5G Transceivers
Ryynänen, J., Boopathy, D. & Ghosh, A.
01/08/2020 → 31/07/2024
Project: EU: MC