Rate-distortion performance analysis of an analog motion estimation array

Lauri Koskinen*, Jonne Poikonen, Mika Laiho, Ari Paasio

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Abstract

Emerging 3D-integration enables integrating high quality image sensors with various massively parallel processing elements. Analog motion estimation is one potential application, which is likely to result in significant benefits in the form of low power or high frame-rate 3D-integrated image sensorprocessors. The system-level operation of a proposed analog motion estimation array, enabling all various block sizes from 4x4 to 16x16 is examined. The analog motion estimation circuitry has been designed as a 32x32 test array in 0.13 μm CMOS technology. The transistor-level simulation results combined with H.264/AVC JM 14.2 show equivalent rate-distortion results with SAD as the error measure and an approximately 7% increase in bitrate with a slight increase in image quality for SSE.

Original languageEnglish
Title of host publication2010 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2010 - Proceedings
Pages1530-1533
Number of pages4
DOIs
Publication statusPublished - 2010
MoE publication typeA4 Article in a conference publication
EventIEEE International Conference on Acoustics, Speech, and Signal Processing - Dallas, United States
Duration: 14 Mar 201019 Mar 2010

Publication series

NameInternational Conference on Acoustics Speech and Signal Processing ICASSP
ISSN (Print)1520-6149

Conference

ConferenceIEEE International Conference on Acoustics, Speech, and Signal Processing
Abbreviated titleICASSP
CountryUnited States
CityDallas
Period14/03/201019/03/2010

Keywords

  • Analog parallel processing
  • H.264
  • Motion estimation

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