Proof Complexity of Cut-Based Tableaux for Boolean Circuit Satisfiability Checking

Matti Järvisalo

    Research output: Working paperProfessional

    Original languageEnglish
    Place of PublicationEspoo
    Publication statusPublished - 2004
    MoE publication typeD4 Published development or research report or study

    Publication series

    NameReport Series A
    PublisherLaboratory for Theoretical Computer Science, Helsinki University of Technology


    • Boolean circuits
    • cut rule
    • Davis-Putnam method
    • polynomial simulation
    • proof complexity
    • propositional satisfiability
    • resolution
    • satisfiability checking

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