TY - JOUR
T1 - Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI
AU - Schmidt, Colin
AU - Amid, Alon
AU - Wright, John
AU - Keller, Ben
AU - Mao, Howard
AU - Settaluri, Keertana
AU - Salomaa, Jarno
AU - Zhao, Jerry
AU - Ou, Albert
AU - Asanović, Krste
AU - Nikolić, Borivoje
PY - 2020/1/1
Y1 - 2020/1/1
N2 - This letter presents a RISC-V System-on-Chip (SoC) with fully integrated switched-capacitor DC-DC converters, adaptive clock generators, mixed-precision floating-point vector accelerators, a 5-Gb/s serial memory interface, and an integrated power management unit (PMU) manufactured in 28-nm FD-SOI. The vector accelerator improves performance and energy per task on a matrix multiplication kernel by 15\times and 13\times , respectively, and end-to-end performance on machine learning and graph analytical workloads by 8\times - 12\times . Inclusion of microarchitectural counters and fine spatial power-domain granularity facilitate the predictive power-management algorithms that reduce energy per task by 13%-22% compared to the baseline scalar processor. System-level simulations of a range of SoC architectural variations with multiple cores and vector accelerators complement the silicon measurements.
AB - This letter presents a RISC-V System-on-Chip (SoC) with fully integrated switched-capacitor DC-DC converters, adaptive clock generators, mixed-precision floating-point vector accelerators, a 5-Gb/s serial memory interface, and an integrated power management unit (PMU) manufactured in 28-nm FD-SOI. The vector accelerator improves performance and energy per task on a matrix multiplication kernel by 15\times and 13\times , respectively, and end-to-end performance on machine learning and graph analytical workloads by 8\times - 12\times . Inclusion of microarchitectural counters and fine spatial power-domain granularity facilitate the predictive power-management algorithms that reduce energy per task by 13%-22% compared to the baseline scalar processor. System-level simulations of a range of SoC architectural variations with multiple cores and vector accelerators complement the silicon measurements.
KW - Dynamic voltage scaling
KW - energy efficiency
KW - microprocessors
KW - system analysis and design
KW - system-on-chip
KW - vector processors
UR - http://www.scopus.com/inward/record.url?scp=85089300168&partnerID=8YFLogxK
U2 - 10.1109/LSSC.2020.3010295
DO - 10.1109/LSSC.2020.3010295
M3 - Article
AN - SCOPUS:85089300168
SN - 2573-9603
VL - 3
SP - 210
EP - 213
JO - IEEE Solid-State Circuits Letters
JF - IEEE Solid-State Circuits Letters
M1 - 9144250
ER -
