Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI

Colin Schmidt, Alon Amid*, John Wright, Ben Keller, Howard Mao, Keertana Settaluri, Jarno Salomaa, Jerry Zhao, Albert Ou, Krste Asanović, Borivoje Nikolić

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

3 Citations (Scopus)


This letter presents a RISC-V System-on-Chip (SoC) with fully integrated switched-capacitor DC-DC converters, adaptive clock generators, mixed-precision floating-point vector accelerators, a 5-Gb/s serial memory interface, and an integrated power management unit (PMU) manufactured in 28-nm FD-SOI. The vector accelerator improves performance and energy per task on a matrix multiplication kernel by 15\times and 13\times , respectively, and end-to-end performance on machine learning and graph analytical workloads by 8\times - 12\times . Inclusion of microarchitectural counters and fine spatial power-domain granularity facilitate the predictive power-management algorithms that reduce energy per task by 13%-22% compared to the baseline scalar processor. System-level simulations of a range of SoC architectural variations with multiple cores and vector accelerators complement the silicon measurements.

Original languageEnglish
Article number9144250
Pages (from-to)210-213
Number of pages4
JournalIEEE Solid-State Circuits Letters
Publication statusPublished - 1 Jan 2020
MoE publication typeA1 Journal article-refereed


  • Dynamic voltage scaling
  • energy efficiency
  • microprocessors
  • system analysis and design
  • system-on-chip
  • vector processors


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