Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. / Vuorinen, Vesa; Ross, Glenn; Viljanen, Heikki; Decker, James; Paulasto-Krockel, Mervi.

Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018. Institute of Electrical and Electronics Engineers, 2018. 8546398.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Vuorinen, V, Ross, G, Viljanen, H, Decker, J & Paulasto-Krockel, M 2018, Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. in Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018., 8546398, Institute of Electrical and Electronics Engineers, Electronic System Integration Technology Conference, Dresden, Germany, 18/09/2018. https://doi.org/10.1109/ESTC.2018.8546398

APA

Vuorinen, V., Ross, G., Viljanen, H., Decker, J., & Paulasto-Krockel, M. (2018). Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. In Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018 [8546398] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESTC.2018.8546398

Vancouver

Vuorinen V, Ross G, Viljanen H, Decker J, Paulasto-Krockel M. Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. In Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018. Institute of Electrical and Electronics Engineers. 2018. 8546398 https://doi.org/10.1109/ESTC.2018.8546398

Author

Vuorinen, Vesa ; Ross, Glenn ; Viljanen, Heikki ; Decker, James ; Paulasto-Krockel, Mervi. / Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018. Institute of Electrical and Electronics Engineers, 2018.

Bibtex - Download

@inproceedings{cddcec3d74334b3eb06314eec613d1ad,
title = "Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS",
abstract = "The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.",
keywords = "MEMS, Process integration, Reliability, Wafer level SLID bonding",
author = "Vesa Vuorinen and Glenn Ross and Heikki Viljanen and James Decker and Mervi Paulasto-Krockel",
year = "2018",
month = "11",
day = "26",
doi = "10.1109/ESTC.2018.8546398",
language = "English",
booktitle = "Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

RIS - Download

TY - GEN

T1 - Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

AU - Vuorinen, Vesa

AU - Ross, Glenn

AU - Viljanen, Heikki

AU - Decker, James

AU - Paulasto-Krockel, Mervi

PY - 2018/11/26

Y1 - 2018/11/26

N2 - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

AB - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

KW - MEMS

KW - Process integration

KW - Reliability

KW - Wafer level SLID bonding

UR - http://www.scopus.com/inward/record.url?scp=85060057433&partnerID=8YFLogxK

U2 - 10.1109/ESTC.2018.8546398

DO - 10.1109/ESTC.2018.8546398

M3 - Conference contribution

BT - Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018

PB - Institute of Electrical and Electronics Engineers

ER -

ID: 31554081