The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.
|Title of host publication||Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018|
|Number of pages||6|
|Publication status||Published - 26 Nov 2018|
|MoE publication type||A4 Article in a conference publication|
|Event||Electronic System Integration Technology Conference - Dresden, Germany|
Duration: 18 Sep 2018 → 21 Sep 2018
Conference number: 7
|Conference||Electronic System Integration Technology Conference|
|Period||18/09/2018 → 21/09/2018|
- Process integration
- Wafer level SLID bonding
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Anna Rissanen (Manager)Aalto University
OtaNano - Nanomicroscopy Center
Jani Seitsonen (Manager)OtaNano