Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Vesa Vuorinen; Glenn Ross; Heikki Viljanen; James Decker; Mervi Paulasto-Krockel

doi:10.1109/ESTC.2018.8546398

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Vesa Vuorinen, Glenn Ross, Heikki Viljanen, James Decker, Mervi Paulasto-Krockel

VTT Technical Research Centre of Finland

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

464 Downloads (Pure)

Abstract

The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

Original language	English
Title of host publication	Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018
Publisher	IEEE
Number of pages	6
ISBN (Electronic)	9781538668139
DOIs	https://doi.org/10.1109/ESTC.2018.8546398
Publication status	Published - 26 Nov 2018
MoE publication type	A4 Conference publication
Event	Electronic System Integration Technology Conference - Dresden, Germany Duration: 18 Sept 2018 → 21 Sept 2018 Conference number: 7

Conference

Conference	Electronic System Integration Technology Conference
Abbreviated title	ESTC
Country/Territory	Germany
City	Dresden
Period	18/09/2018 → 21/09/2018

Keywords

MEMS
Process integration
Reliability
Wafer level SLID bonding

Access to Document

10.1109/ESTC.2018.8546398

ELEC_Vuorinen_etal_Process-Integration-and-Reliability_ESTC_2018Final published version, 800 KB

Cite this

@inproceedings{cddcec3d74334b3eb06314eec613d1ad,

title = "Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS",

abstract = "The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.",

keywords = "MEMS, Process integration, Reliability, Wafer level SLID bonding",

author = "Vesa Vuorinen and Glenn Ross and Heikki Viljanen and James Decker and Mervi Paulasto-Krockel",

year = "2018",

month = nov,

day = "26",

doi = "10.1109/ESTC.2018.8546398",

language = "English",

booktitle = "Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018",

publisher = "IEEE",

address = "United States",

note = "Electronic System Integration Technology Conference, ESTC ; Conference date: 18-09-2018 Through 21-09-2018",

}

Vuorinen, V , Ross, G, Viljanen, H, Decker, J & Paulasto-Krockel, M 2018, Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. in Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018., 8546398, IEEE, Electronic System Integration Technology Conference, Dresden, Saxony, Germany, 18/09/2018. https://doi.org/10.1109/ESTC.2018.8546398

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. / Vuorinen, Vesa ; Ross, Glenn; Viljanen, Heikki et al.
Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018. IEEE, 2018. 8546398.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

AU - Vuorinen, Vesa

AU - Ross, Glenn

AU - Viljanen, Heikki

AU - Decker, James

AU - Paulasto-Krockel, Mervi

N1 - Conference code: 7

PY - 2018/11/26

Y1 - 2018/11/26

N2 - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

AB - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.'vias before bonding' capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

KW - MEMS

KW - Process integration

KW - Reliability

KW - Wafer level SLID bonding

UR - http://www.scopus.com/inward/record.url?scp=85060057433&partnerID=8YFLogxK

U2 - 10.1109/ESTC.2018.8546398

DO - 10.1109/ESTC.2018.8546398

M3 - Conference article in proceedings

AN - SCOPUS:85060057433

BT - Proceedings of the 2018 7th Electronic System-Integration Technology Conference, ESTC 2018

PB - IEEE

T2 - Electronic System Integration Technology Conference

Y2 - 18 September 2018 through 21 September 2018

ER -

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

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Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

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