Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit ΔΣ RF-DAC in 16-nm FinFET

Research output: Contribution to journalArticleScientificpeer-review

Researchers

Research units

  • Huawei Technologies
  • Huawei Technologies

Abstract

This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any bias tuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode.

Details

Original languageEnglish
Pages (from-to)126-129
Number of pages4
JournalIEEE Solid State Circuits Letters
Volume1
Issue number5
Publication statusPublished - 2018
MoE publication typeA1 Journal article-refereed

    Research areas

  • Modulation, Power demand, Solid state circuits, Gain control, Multiplexing, Radio frequency, Radio transmitters, Delta–sigma modulation, digital gain control, dynamic element matching (DEM), power back-off, RF-DAC

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