Partitioning and macromodel-based model-order reduction for RLC circuits

Pekka Miettinen

    Research output: ThesisLicenciate's thesis

    Original languageEnglish
    QualificationLicentiate's degree
    Awarding Institution
    • Aalto University
    Supervisors/Advisors
    • Valtonen, Martti, Supervising Professor
    • Roos, Janne, Thesis Advisor
    Publisher
    Publication statusPublished - 2010
    MoE publication typeG3 Licentiate thesis

    Keywords

    • Circuit simulation
    • Interconnect modeling
    • Model-order reduction
    • Hierarchical analysis
    • Circuit partitioning
    • RLC
    • RC
    • RL
    • PartMOR

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