Open-loop all-digital delay line with on-chip calibration via self-equalizing delays

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Research units


A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the external period and reference delay is then readjusted. When on-board settling monitor observes repetition of reference delay settings, it locks delay line by applying previously collected settings. The delay line is shown to lock in presence of 30% static offset of delays from their designed values. Furthermore, random spread of delays worsened by 3 times (5% PP to 15% PP ) results in only 2% decline (3% PP to 5% PP ) after applying the proposed calibration to 16-delays line.


Original languageEnglish
Title of host publication23rd European Conference on Circuit Theory and Design (ECCTD 2017)
Publication statusPublished - 2017
MoE publication typeA4 Article in a conference publication
EventEuropean Conference on Circuit Theory and Design - Università degli Studi di Catania - Piazza Università, 2 - 95131 Catania, Catania, Italy
Duration: 4 Sep 20176 Sep 2017
Conference number: 23

Publication series

NameEuropean Conference on Circuit Theory and Design
ISSN (Electronic)2474-9672


ConferenceEuropean Conference on Circuit Theory and Design
Abbreviated titleECCTD
Internet address

ID: 15323735