Abstract
Chiplet-based CPUs, which combine multiple independent dies on a single package, allow hardware to scale to higher CPU core counts at the cost of more memory heterogeneity and performance variability. This introduces challenges when existing query engines are deployed on chiplet-based CPUs, as current designs make assumptions about uniform memory access, cache locality and consistent core performance,e.g., leading to in effective CPU utilization. In this paper, we analyse the performance impact when query engine sign orechiplet-specific properties. We demonstrate that a naïve deployment can result in significant degradation of query processing efficiency, exhibiting non-linear scaling even with in a single CPU socket domain. Based on comprehensive experiments, we explore approaches to deploy query engines on chiplet-based CPUs with improved performance: we show that distributing processing tasks according to achiplet-aware strategy achieves higher resource utilization and scalability, yielding an upto7×speedup compared to hardware-oblivious approaches.
Original language | English |
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Pages (from-to) | 3428-3441 |
Number of pages | 14 |
Journal | Proceedings of the VLDB Endowment |
Volume | 17 |
Issue number | 11 |
DOIs | |
Publication status | Published - 2024 |
MoE publication type | A4 Conference publication |
Event | International Conference on Very Large Data Bases - Guangzhou, China Duration: 24 Aug 2024 → 29 Aug 2024 Conference number: 50 |