Nonmonotone Norm-Reduction Method for Circuit Simulation

M. Honkala

Nonmonotone Norm-Reduction Method for Circuit Simulation

M. Honkala

Research output: Contribution to journal › Article › Scientific › peer-review

Original language	English
Pages (from-to)	1316-1317
Journal	Electronics Letters
Volume	38
Issue number	22
Publication status	Published - 2002
MoE publication type	A1 Journal article-refereed

Keywords

APLAC
circuit simulation
convergence
nonmonotone

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@article{efe7caa3b75049f380cf62134e207b02,

title = "Nonmonotone Norm-Reduction Method for Circuit Simulation",

keywords = "APLAC, circuit simulation, convergence, nonmonotone, APLAC, circuit simulation, convergence, nonmonotone, APLAC, circuit simulation, convergence, nonmonotone",

author = "M. Honkala",

year = "2002",

language = "English",

volume = "38",

pages = "1316--1317",

journal = "Electronics Letters",

issn = "1350-911X",

publisher = "Institution of Engineering and Technology",

number = "22",

}

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T1 - Nonmonotone Norm-Reduction Method for Circuit Simulation

AU - Honkala, M.

PY - 2002

Y1 - 2002

KW - APLAC

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KW - convergence

KW - nonmonotone

KW - APLAC

KW - circuit simulation

KW - convergence

KW - nonmonotone

KW - APLAC

KW - circuit simulation

KW - convergence

KW - nonmonotone

M3 - Article

SN - 1350-911X

VL - 38

SP - 1316

EP - 1317

JO - Electronics Letters

JF - Electronics Letters

IS - 22

ER -