Abstract
Copper (Cu) impurities are known to cause harmful light-induced degradation (Cu-LID) in p-type silicon, even when present in 1E10 cm-3 concentrations. Therefore, it is important to be able to control Cu impurities during device fabrication. In case Cu impurities cannot be fully avoided, the most obvious way to mitigate Cu-LID is gettering, i.e. relocation of Cu impurities from the active device areas to locations in which they are not harmful. Due to high diffusivity of copper, such relocation is expected to be relatively simple as compared to slow-diffusing impurities.
Here we report our experimental findings on the gettering of Cu and its impact on Cu-LID effects and demonstrate that e.g. the standard phosphorus gettering does not always prevent the occurrence of Cu-LID. Specifically, time-temperature profiles of the device process steps, copper contamination level as well as bulk micro defects present in the wafers play a critical role in the final gettering efficiency. For instance, we show that a typical rapid thermal anneal (RTA, a few seconds at 800 ºC) used commonly in the semiconductor and photovoltaic industries is sufficient to release significant amount of Cu impurities from the phosphorus-doped layer back to the wafer bulk in seemingly gettered wafers.
We also study the impact of Cu-LID on final device operation, namely silicon solar cells, which are processed in industrial environment. We carefully contaminate Cz-substrates of different quality with different amounts of copper and process the substrates into complete industrial Cz-Si solar cells. We demonstrate that copper can be present in significant concentrations in the bulk of the finished cells after being exposed to only trace surface contamination. Consequently, even a small local copper contamination area is sufficient to induce strong LID in the full-sized (8 inch) cell parameters, resulting e.g. in ~7% relative efficiency loss during illumination.
Here we report our experimental findings on the gettering of Cu and its impact on Cu-LID effects and demonstrate that e.g. the standard phosphorus gettering does not always prevent the occurrence of Cu-LID. Specifically, time-temperature profiles of the device process steps, copper contamination level as well as bulk micro defects present in the wafers play a critical role in the final gettering efficiency. For instance, we show that a typical rapid thermal anneal (RTA, a few seconds at 800 ºC) used commonly in the semiconductor and photovoltaic industries is sufficient to release significant amount of Cu impurities from the phosphorus-doped layer back to the wafer bulk in seemingly gettered wafers.
We also study the impact of Cu-LID on final device operation, namely silicon solar cells, which are processed in industrial environment. We carefully contaminate Cz-substrates of different quality with different amounts of copper and process the substrates into complete industrial Cz-Si solar cells. We demonstrate that copper can be present in significant concentrations in the bulk of the finished cells after being exposed to only trace surface contamination. Consequently, even a small local copper contamination area is sufficient to induce strong LID in the full-sized (8 inch) cell parameters, resulting e.g. in ~7% relative efficiency loss during illumination.
| Original language | English |
|---|---|
| DOIs | |
| Publication status | Published - 2018 |
| MoE publication type | Not Eligible |
| Event | Electrochemical Society Meeting and AiMES Meeting - Cancun, Mexico Duration: 30 Sept 2018 → 4 Oct 2018 |
Conference
| Conference | Electrochemical Society Meeting and AiMES Meeting |
|---|---|
| Abbreviated title | ECS/AiMES |
| Country/Territory | Mexico |
| City | Cancun |
| Period | 30/09/2018 → 04/10/2018 |
