Abstract
This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.
Original language | English |
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Title of host publication | Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017 |
Publisher | IEEE |
Pages | 1-4 |
Number of pages | 4 |
Volume | Part F134116 |
ISBN (Electronic) | 9781509065059 |
DOIs | |
Publication status | Published - 4 Jan 2018 |
MoE publication type | A4 Article in a conference publication |
Event | IEEE International Conference on Emerging Technologies and Factory Automation - Limassol, Cyprus Duration: 12 Sep 2017 → 15 Sep 2017 Conference number: 22 |
Publication series
Name | Proceedings IEEE International Conference on Emerging Technologies and Factory Automation |
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Publisher | IEEE |
ISSN (Print) | 1946-0740 |
ISSN (Electronic) | 2379-9560 |
Conference
Conference | IEEE International Conference on Emerging Technologies and Factory Automation |
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Abbreviated title | ETFA |
Country | Cyprus |
City | Limassol |
Period | 12/09/2017 → 15/09/2017 |
Keywords
- Delaunay triangulation
- Field programmable gate array
- High-level synthesis
- Pipelining
- Register-Transfer-level
- Surface reconstruction