Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis

Christakis Kallis, Kyriakos M. Deliparaschos, George P. Moustris, Avraam Georgiou, Themistoklis Charalambous

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

3 Citations (Scopus)

Abstract

This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.

Original languageEnglish
Title of host publicationProceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017
PublisherIEEE
Pages1-4
Number of pages4
VolumePart F134116
ISBN (Electronic)9781509065059
DOIs
Publication statusPublished - 4 Jan 2018
MoE publication typeA4 Article in a conference publication
EventIEEE International Conference on Emerging Technologies and Factory Automation - Limassol, Cyprus
Duration: 12 Sep 201715 Sep 2017
Conference number: 22

Publication series

NameProceedings IEEE International Conference on Emerging Technologies and Factory Automation
PublisherIEEE
ISSN (Print)1946-0740
ISSN (Electronic)2379-9560

Conference

ConferenceIEEE International Conference on Emerging Technologies and Factory Automation
Abbreviated titleETFA
CountryCyprus
CityLimassol
Period12/09/201715/09/2017

Keywords

  • Delaunay triangulation
  • Field programmable gate array
  • High-level synthesis
  • Pipelining
  • Register-Transfer-level
  • Surface reconstruction

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  • Cite this

    Kallis, C., Deliparaschos, K. M., Moustris, G. P., Georgiou, A., & Charalambous, T. (2018). Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis. In Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017 (Vol. Part F134116, pp. 1-4). (Proceedings IEEE International Conference on Emerging Technologies and Factory Automation). IEEE. https://doi.org/10.1109/ETFA.2017.8247736