Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis

Christakis Kallis; Kyriakos M. Deliparaschos; George P. Moustris; Avraam Georgiou; Themistoklis Charalambous

doi:10.1109/ETFA.2017.8247736

Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis

Christakis Kallis, Kyriakos M. Deliparaschos, George P. Moustris, Avraam Georgiou, Themistoklis Charalambous

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

Abstract

This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.

Original language	English
Title of host publication	Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017
Publisher	IEEE
Pages	1-4
Number of pages	4
Volume	Part F134116
ISBN (Electronic)	9781509065059
DOIs	https://doi.org/10.1109/ETFA.2017.8247736
Publication status	Published - 4 Jan 2018
MoE publication type	A4 Article in a conference publication
Event	IEEE International Conference on Emerging Technologies and Factory Automation - Limassol, Cyprus Duration: 12 Sep 2017 → 15 Sep 2017 Conference number: 22

Publication series

Name	Proceedings IEEE International Conference on Emerging Technologies and Factory Automation
Publisher	IEEE
ISSN (Print)	1946-0740
ISSN (Electronic)	2379-9560

Conference

Conference	IEEE International Conference on Emerging Technologies and Factory Automation
Abbreviated title	ETFA
Country	Cyprus
City	Limassol
Period	12/09/2017 → 15/09/2017

Keywords

Delaunay triangulation
Field programmable gate array
High-level synthesis
Pipelining
Register-Transfer-level
Surface reconstruction

Access to Document

10.1109/ETFA.2017.8247736

Link to publication in Scopus

Fingerprint Dive into the research topics of 'Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis'. Together they form a unique fingerprint.

Cite this

Kallis, C., Deliparaschos, K. M., Moustris, G. P., Georgiou, A., & Charalambous, T. (2018). Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis. In Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017 (Vol. Part F134116, pp. 1-4). (Proceedings IEEE International Conference on Emerging Technologies and Factory Automation). IEEE. https://doi.org/10.1109/ETFA.2017.8247736

Kallis, Christakis ; Deliparaschos, Kyriakos M. ; Moustris, George P. ; Georgiou, Avraam ; Charalambous, Themistoklis. / Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis. Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017. Vol. Part F134116 IEEE, 2018. pp. 1-4 (Proceedings IEEE International Conference on Emerging Technologies and Factory Automation).

@inproceedings{1f3c8f50923749f7b3d43af822d27b15,

title = "Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis",

abstract = "This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.",

keywords = "Delaunay triangulation, Field programmable gate array, High-level synthesis, Pipelining, Register-Transfer-level, Surface reconstruction",

author = "Christakis Kallis and Deliparaschos, {Kyriakos M.} and Moustris, {George P.} and Avraam Georgiou and Themistoklis Charalambous",

year = "2018",

month = "1",

day = "4",

doi = "10.1109/ETFA.2017.8247736",

language = "English",

volume = "Part F134116",

series = "Proceedings IEEE International Conference on Emerging Technologies and Factory Automation",

publisher = "IEEE",

pages = "1--4",

booktitle = "Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017",

address = "United States",

}

Kallis, C, Deliparaschos, KM, Moustris, GP, Georgiou, A & Charalambous, T 2018, Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis. in Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017. vol. Part F134116, Proceedings IEEE International Conference on Emerging Technologies and Factory Automation, IEEE, pp. 1-4, IEEE International Conference on Emerging Technologies and Factory Automation, Limassol, Cyprus, 12/09/2017. https://doi.org/10.1109/ETFA.2017.8247736

Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis. / Kallis, Christakis; Deliparaschos, Kyriakos M.; Moustris, George P.; Georgiou, Avraam; Charalambous, Themistoklis.

Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017. Vol. Part F134116 IEEE, 2018. p. 1-4 (Proceedings IEEE International Conference on Emerging Technologies and Factory Automation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis

AU - Kallis, Christakis

AU - Deliparaschos, Kyriakos M.

AU - Moustris, George P.

AU - Georgiou, Avraam

AU - Charalambous, Themistoklis

PY - 2018/1/4

Y1 - 2018/1/4

N2 - This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.

AB - This paper presents a 2D Delaunay triangulation core for surface reconstruction implemented on a Field Programmable Gate Array (FPGA) chip. The core implementation is derived using high-level synthesis from a C++ description of an incremental 2D Delaunay triangulation algorithm. This description was modified accordingly so that it can be embedded into a FPGA chip using hardware description language. Goal of this work is to increase the execution speed of the algorithm so as to allow for real-time operation. Towards this end, we performed an optimization process using high level synthesis directives which pipeline regions of the code in order to achieve delay optimization. We show preliminary results using standard benchmark models for surface reconstruction, which show the performance of our design.

KW - Delaunay triangulation

KW - Field programmable gate array

KW - High-level synthesis

KW - Pipelining

KW - Register-Transfer-level

KW - Surface reconstruction

UR - http://www.scopus.com/inward/record.url?scp=85044458836&partnerID=8YFLogxK

U2 - 10.1109/ETFA.2017.8247736

DO - 10.1109/ETFA.2017.8247736

M3 - Conference contribution

AN - SCOPUS:85044458836

VL - Part F134116

T3 - Proceedings IEEE International Conference on Emerging Technologies and Factory Automation

SP - 1

EP - 4

BT - Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017

PB - IEEE

ER -

Kallis C, Deliparaschos KM, Moustris GP, Georgiou A, Charalambous T. Incremental 2D delaunay triangulation core implementation on FPGA for surface reconstruction via high-level synthesis. In Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2017. Vol. Part F134116. IEEE. 2018. p. 1-4. (Proceedings IEEE International Conference on Emerging Technologies and Factory Automation). https://doi.org/10.1109/ETFA.2017.8247736