@techreport{31dd92430b2a42928c745fc50384b502,
title = "Improving the speed and convergence of DC analysis by means of self-generating lookup tables and piecewise-linear analysis",
keywords = "APLAC, circuit simulation, DC analysis, interpolation, lookup tables, numerical methods, APLAC, circuit simulation, DC analysis, interpolation, lookup tables, numerical methods, APLAC, circuit simulation, DC analysis, interpolation, lookup tables, numerical methods",
author = "J. Roos",
year = "1999",
language = "English",
series = "Acta Polytechnica Scandinavica Electrical Engineering Series",
publisher = "The Finnish Academy of Technology",
number = "No. 99",
pages = "108",
type = "WorkingPaper",
institution = "The Finnish Academy of Technology",
}