Improving the speed and convergence of DC analysis by means of self-generating lookup tables and piecewise-linear analysis

J. Roos

    Research output: Working paperProfessional

    1 Citation (Scopus)
    Original languageEnglish
    Place of PublicationEspoo
    Pages108
    Publication statusPublished - 1999
    MoE publication typeD4 Published development or research report or study

    Publication series

    NameActa Polytechnica Scandinavica Electrical Engineering Series
    PublisherThe Finnish Academy of Technology
    No.No. 99

    Keywords

    • APLAC
    • circuit simulation
    • DC analysis
    • interpolation
    • lookup tables
    • numerical methods

    Cite this

    Roos, J. (1999). Improving the speed and convergence of DC analysis by means of self-generating lookup tables and piecewise-linear analysis. (pp. 108). (Acta Polytechnica Scandinavica Electrical Engineering Series; No. No. 99).