Nowadays, a high-speed medium-accuracy analog-to-digital converter (ADC) is required in numerous applications, such as a synthetic aperture radar (SAR) system, wireless local area network (WLAN) receiver, or DVD and Blu-Ray readout. As one of the two main parts, this dissertation presents the design and implementation of wideband high-speed medium-accuracy pipeline ADC as a part of a receiver of a SAR system, implemented in a deep-submicron CMOS process. Technology scaling of modern narrow line width CMOS processes has enabled higher bandwidths, but from dynamic range and accuracy perspectives, analog design of integrated circuits has become more challenging. This thesis presents detailed design of the critical analog circuit blocks of the pipeline ADC, covering two fabricated 130-nm 440-MS/s programmable 5-8-bit ADC prototypes for a SAR receiver. Due to their flexibility, the ADCs can be optimized for several standards in accordance with the accuracy and power. The second ADC was also measured together with the entire receiver. The ADC discussion of this thesis is twofold, and the SAR receiver discussion is followed by a design case of an ADC for pressure sensors, where low power and high accuracy are required. The design and measurements of a 350-nm 28-microwatt 14-bit 16-kS/s Delta Sigma modulator are presented. Adequate accuracy and low consumption of total system power make the modulator a very suitable structure for this indicated application. The other main part of this thesis consists of high-speed IO drivers in modern wideband transceivers. Nowadays, multi-functional mobile phones need to be of a compact size, and thus serial link wireline IO drivers are tempting alternatives to be used for the internal communication. This leads to very rapid data rates and a challenging EMI environment in proximity to the IO, and the coupling of EMI to radio receivers inside the same device becomes critical. Furthermore, in a battery-powered system the power consumption should be minimized. Conventional current-mode drivers can achieve very low output noise, at a cost of several times higher power consumption compared to voltage-mode drivers. This thesis presents the design and measurement results of a 200-400-mV 5.8-Gbps 40-nm CMOS voltage-mode transmitter driver consuming inherently low power. As an original research work, the measurements show sufficiently low output noise, making the driver a suitable structure to be used in mobile devices. The high-speed IO driver discussion is completed with design examples of an 8-Gbps LVDS input data interface and an 8-GHz local oscillator signal buffer and divider for a LTE base station transmitter.
|Translated title of the contribution||Korkean suorituskyvyn A/D-muuntimia ja siirtolinjan ajamiseen suunniteltuja ajureita|
|Publication status||Published - 2016|
|MoE publication type||G4 Doctoral dissertation (monograph)|
- pipeline A/D converter
- Delta-Sigma A/D converter
- serial link
- IO driver