Hardware efficient design of variable length FFT processor

Vinay Gautam; Kailash Chandra Ray; Pauline Haddow

doi:10.1109/DDECS.2011.5783102

Hardware efficient design of variable length FFT processor

Vinay Gautam^*, Kailash Chandra Ray, Pauline Haddow

^*Corresponding author for this work

Not published at Aalto University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

14 Citations (Scopus)

Abstract

Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2ⁿ (n=6, 7.....13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). The solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. The key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage; a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.

Original language	English
Title of host publication	Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011
Pages	309-312
Number of pages	4
DOIs	https://doi.org/10.1109/DDECS.2011.5783102
Publication status	Published - 11 Jul 2011
MoE publication type	A4 Article in a conference publication
Event	IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - Cottbus, Germany Duration: 13 Apr 2011 → 15 Apr 2011 Conference number: 14

Conference

Conference	IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Abbreviated title	DDECS
Country/Territory	Germany
City	Cottbus
Period	13/04/2011 → 15/04/2011

Keywords

Dynamic Address Generator
FFT
OFDM
Pipelined CORDIC

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10.1109/DDECS.2011.5783102

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title = "Hardware efficient design of variable length FFT processor",

abstract = "Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2n (n=6, 7.....13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). The solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. The key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage; a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.",

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Gautam, V, Ray, KC & Haddow, P 2011, Hardware efficient design of variable length FFT processor. in Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011., 5783102, pp. 309-312, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, Germany, 13/04/2011. https://doi.org/10.1109/DDECS.2011.5783102

Hardware efficient design of variable length FFT processor. / Gautam, Vinay; Ray, Kailash Chandra; Haddow, Pauline.

Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. p. 309-312 5783102.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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Hardware efficient design of variable length FFT processor

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Keywords

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