Fractional-N open-loop digital frequency synthesizer with a post-modulator for jitter reduction

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Researchers

Research units

  • TDK Nordic

Abstract

This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.

Details

Original languageEnglish
Title of host publicationRFIC 2016 - 2016 IEEE Radio Frequency Integrated Circuits Symposium
Publication statusPublished - 8 Jul 2016
MoE publication typeA4 Article in a conference publication
EventIEEE Radio Frequency Integrated Circuits Symposium - San Francisco, United States
Duration: 22 May 201624 May 2016

Publication series

NameIEEE Radio Frequency Integrated Circuits Symposium
PublisherIEEE
ISSN (Print)1529-2517

Conference

ConferenceIEEE Radio Frequency Integrated Circuits Symposium
Abbreviated titleRFIC
CountryUnited States
CitySan Francisco
Period22/05/201624/05/2016

    Research areas

  • delay modulator, fractional-N frequency synthesizer, multiplying delay-locked loop (MDLL)

ID: 6808491