This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.