FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

A. Chariete; M. Bakhouya; J. Gaber; M. Wack

doi:10.1109/HPCSim.2013.6641416

FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

A. Chariete
, M. Bakhouya
, J. Gaber
, M. Wack

Department of Energy and Mechanical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget.

Original language	English
Title of host publication	Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
Pages	213-216
Number of pages	4
DOIs	https://doi.org/10.1109/HPCSim.2013.6641416
Publication status	Published - 2013
MoE publication type	A4 Conference publication
Event	International Conference on High Performance Computing & Simulation - Helsinki, Finland Duration: 1 Jul 2013 → 5 Jul 2013 Conference number: 11

Conference

Conference	International Conference on High Performance Computing & Simulation
Abbreviated title	HPCS
Country/Territory	Finland
City	Helsinki
Period	01/07/2013 → 05/07/2013

Keywords

Fractal structures
Network on Chip
Nirgam
performance evaluation
simulations
System on Chip

Access to Document

10.1109/HPCSim.2013.6641416

Cite this

@inproceedings{389606b5fd244e8682f10143defeb4d4,

title = "FracNoC: A fractal on-chip interconnect architecture for System-on-Chip",

abstract = "Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget.",

keywords = "Fractal structures, Network on Chip, Nirgam, performance evaluation, simulations, System on Chip",

author = "A. Chariete and M. Bakhouya and J. Gaber and M. Wack",

year = "2013",

doi = "10.1109/HPCSim.2013.6641416",

language = "English",

isbn = "9781479908363",

pages = "213--216",

booktitle = "Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013",

note = "International Conference on High Performance Computing \& Simulation, HPCS ; Conference date: 01-07-2013 Through 05-07-2013",

}

Chariete, A, Bakhouya, M, Gaber, J & Wack, M 2013, FracNoC: A fractal on-chip interconnect architecture for System-on-Chip. in Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013., 6641416, pp. 213-216, International Conference on High Performance Computing & Simulation, Helsinki, Finland, 01/07/2013. https://doi.org/10.1109/HPCSim.2013.6641416

FracNoC: A fractal on-chip interconnect architecture for System-on-Chip. / Chariete, A.; Bakhouya, M.; Gaber, J. et al.
Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013. 2013. p. 213-216 6641416.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - FracNoC

T2 - International Conference on High Performance Computing & Simulation

AU - Chariete, A.

AU - Bakhouya, M.

AU - Gaber, J.

AU - Wack, M.

N1 - Conference code: 11

PY - 2013

Y1 - 2013

N2 - Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget.

AB - Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget.

KW - Fractal structures

KW - Network on Chip

KW - Nirgam

KW - performance evaluation

KW - simulations

KW - System on Chip

UR - https://www.scopus.com/pages/publications/84888071014

U2 - 10.1109/HPCSim.2013.6641416

DO - 10.1109/HPCSim.2013.6641416

M3 - Conference article in proceedings

AN - SCOPUS:84888071014

SN - 9781479908363

SP - 213

EP - 216

BT - Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013

Y2 - 1 July 2013 through 5 July 2013

ER -

FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this