FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

A. Chariete, M. Bakhouya, J. Gaber, M. Wack

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

3 Citations (Scopus)

Abstract

Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget.

Original languageEnglish
Title of host publicationProceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
Pages213-216
Number of pages4
DOIs
Publication statusPublished - 2013
MoE publication typeA4 Article in a conference publication
EventInternational Conference on High Performance Computing & Simulation - Helsinki, Finland
Duration: 1 Jul 20135 Jul 2013
Conference number: 11

Conference

ConferenceInternational Conference on High Performance Computing & Simulation
Abbreviated titleHPCS
CountryFinland
CityHelsinki
Period01/07/201305/07/2013

Keywords

  • Fractal structures
  • Network on Chip
  • Nirgam
  • performance evaluation
  • simulations
  • System on Chip

Fingerprint

Dive into the research topics of 'FracNoC: A fractal on-chip interconnect architecture for System-on-Chip'. Together they form a unique fingerprint.

Cite this