FPGA-based implementation of a 59-neuron feedforward neural network with a 17.1 Gbps interlayer throughput

Antti Hämäläinen*, Matti Tommiska, Jorma Skyttä

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Abstract

This paper presents a Field Programmable Gate Array (FPGA) based implementation of a large-scale digital feedforward neural network. The finite wordlength effects of truncated number representations were extensively analyzed prior to the hardware design stage in order to achieve similar performance as with the original software-based neural network. The implemented four-layer 59-neuron network fits into a Xilinx XC2V8000 device and operates at a clock frequency of 45 MHz, which corresponds to an interlayer throughput of 17.1 gigabus per second. The benefits of FPGA-based neural network implementations include reprogrammability, parallel implementation and suitability for real-time applications.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Artificial Intelligence, IC-AI'04
EditorsH.R. Arabnia, Y Mun
Pages181-187
Number of pages7
Publication statusPublished - 2004
MoE publication typeA4 Article in a conference publication
EventInternational Conference on Artificial Intelligence - Las Vegas, United States
Duration: 21 Jun 200424 Jun 2004

Conference

ConferenceInternational Conference on Artificial Intelligence
Abbreviated titleIC-AI
CountryUnited States
CityLas Vegas
Period21/06/200424/06/2004

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