Finite element modeling for reliability assessment of solder interconnections in a power transistor

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Original language	English
Title of host publication	ESTC 4th Electronic System-Integration Technology Conference, Sept. 17-20, 2012, Amsterdam
Publisher	IEEE
ISBN (Print)	978-1-4673-4645-0
Publication status	Published - 2012
MoE publication type	A4 Conference publication

Cite this

@inproceedings{5b3ca7cf068c4917aa17a261582b09e7,

title = "Finite element modeling for reliability assessment of solder interconnections in a power transistor",

author = "Jue Li and Juha Karppinen and Tomi Laurila and Vesa Vuorinen and {Paulasto -Kr{\"o}ckel}, Mervi",

year = "2012",

language = "English",

isbn = "978-1-4673-4645-0",

booktitle = "ESTC 4th Electronic System-Integration Technology Conference, Sept. 17-20, 2012, Amsterdam",

publisher = "IEEE",

address = "United States",

}

Finite element modeling for reliability assessment of solder interconnections in a power transistor. / Li, Jue; Karppinen, Juha; Laurila, Tomi et al.
ESTC 4th Electronic System-Integration Technology Conference, Sept. 17-20, 2012, Amsterdam. IEEE, 2012.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Finite element modeling for reliability assessment of solder interconnections in a power transistor

AU - Li, Jue

AU - Karppinen, Juha

AU - Laurila, Tomi

AU - Vuorinen, Vesa

AU - Paulasto -Kröckel, Mervi

PY - 2012

Y1 - 2012

UR - http://dx.doi.org/10.1109/ESTC.2012.6542121

M3 - Conference article in proceedings

SN - 978-1-4673-4645-0

BT - ESTC 4th Electronic System-Integration Technology Conference, Sept. 17-20, 2012, Amsterdam

PB - IEEE

ER -