TY - JOUR
T1 - Fault-Tolerant Operation Strategy for Reliability Improvement of a Switched-Capacitor Multi-Level Inverter
AU - Hassani, Mohammadjavad
AU - Azimi, Erfan
AU - Khodaparast, Aryorad
AU - Adabi, Jafar
AU - Pouresmaeil, Edris
PY - 2021/12/21
Y1 - 2021/12/21
N2 - the necessity of using several circuit components in Multi-Level Inverters jeopardizes the reliability of operation. Hence, the aim of this research is to propose a novel single-phase fault-tolerant topology based on the Switched-Capacitor concept to ensure the robustness of the converter in the occurrence of a fault. The proposed single source converter steps up the input voltage seven times with a simple control strategy. Fault Tolerance of the converter is achieved by considering multiple fault cases and providing several redundant switching schemes concerning the type and location of failure. Each switching scheme is designed in a way to ensure the ability to tolerate both single and multiple open and short circuit switch failure, achieving self-balance of the capacitors voltages and the same amount of voltage levels and amplitude in the output. Experimental analysis is carried out, and the results confirm the viability of the proposed inverter under normal and post fault operating mode.
AB - the necessity of using several circuit components in Multi-Level Inverters jeopardizes the reliability of operation. Hence, the aim of this research is to propose a novel single-phase fault-tolerant topology based on the Switched-Capacitor concept to ensure the robustness of the converter in the occurrence of a fault. The proposed single source converter steps up the input voltage seven times with a simple control strategy. Fault Tolerance of the converter is achieved by considering multiple fault cases and providing several redundant switching schemes concerning the type and location of failure. Each switching scheme is designed in a way to ensure the ability to tolerate both single and multiple open and short circuit switch failure, achieving self-balance of the capacitors voltages and the same amount of voltage levels and amplitude in the output. Experimental analysis is carried out, and the results confirm the viability of the proposed inverter under normal and post fault operating mode.
UR - http://www.scopus.com/inward/record.url?scp=85122074138&partnerID=8YFLogxK
U2 - 10.1109/TIE.2021.3135623
DO - 10.1109/TIE.2021.3135623
M3 - Article
JO - IEEE Transactions on Industrial Electronics
JF - IEEE Transactions on Industrial Electronics
SN - 0278-0046
ER -