Abstract
Instances of logical cryptanalysis, circuit verification, and bounded model checking can often be succinctly represented as a combined satisfiability (SAT) problem where an instance is a combination of traditional clauses and parity constraints. This paper studies how such combined problems can be efficiently solved by augmenting a modern SAT solver with an xor-reasoning module in the DPLL(XOR) framework. A new xor-reasoning module that deduces all possible implied literals using incremental Gauss-Jordan elimination is presented. A decomposition technique that can greatly reduce the size of parity constraint matrices while still allowing to deduce all implied literals is presented. It is shown how to eliminate variables occuring only in parity constraints while preserving the decomposition. The proposed techniques are evaluated experimentally.
Original language | English |
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Title of host publication | 2012 IEEE 24th International Conference on Tools with Artificial Intelligence, ICTAI 2012 |
Publisher | IEEE |
Pages | 65-72 |
Number of pages | 8 |
Volume | 1 |
ISBN (Print) | 978-1-4799-0227-9, 9780769549156 |
DOIs | |
Publication status | Published - 2012 |
MoE publication type | A4 Conference publication |
Event | IEEE International Conference on Tools with Artificial Intelligence - Athens, Greece Duration: 7 Nov 2012 → 9 Nov 2012 Conference number: 24 |
Publication series
Name | Proceedings-International Conference on Tools With Artificial Intelligence |
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Publisher | IEEE |
ISSN (Print) | 1082-3409 |
Conference
Conference | IEEE International Conference on Tools with Artificial Intelligence |
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Abbreviated title | ICTAI |
Country/Territory | Greece |
City | Athens |
Period | 07/11/2012 → 09/11/2012 |
Keywords
- DPLL(T)