Evaluating an Analog Main Memory Architecture for All-Analog In-Memory Computing Accelerators

Kazybek Adam*, Dipesh Monga, Omar Numan, Gaurav Singh, Kari Halonen, Martin Andraud

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

Analog in memory Computing (IMC) has emerged as a promising method to accelerate deep neural networks (DNNs) on hardware efficiently. Yet, analog computation typically focuses on the multiply and accumulate operation, while other operations are still being computed digitally. Hence, these mixed-signal IMC cores require extensive use of data converters, which can take a third of the total energy and area consumption. Alternatively, all-analog DNN computation is possible but requires increasingly challenging analog storage solutions, due to noise and leakage of advanced technologies. To enable all-analog DNN acceleration, this work demonstrates a feasible IMC architecture using an efficient analog main memory (AMM) cell. The proposed AMM cell is 42x and 5x more power and area efficient than a baseline analog storage cell. An all-analog architecture using this cell achieves potential efficiency gains of 15x compared with a mixed-signal IMC core using data converters.

Original languageEnglish
Title of host publication2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings
PublisherIEEE
Pages248-252
Number of pages5
ISBN (Electronic)979-8-3503-8363-8
DOIs
Publication statusPublished - 2024
MoE publication typeA4 Conference publication
EventIEEE International Conference on AI Circuits and Systems - Abu Dhabi, United Arab Emirates
Duration: 22 Apr 202425 Apr 2024
Conference number: 6

Conference

ConferenceIEEE International Conference on AI Circuits and Systems
Abbreviated titleAICAS
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period22/04/202425/04/2024

Keywords

  • Analog in memory Computing
  • Analog Memory

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