Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm

Zulfiqar Ali; Ali Arshad; Umair Razzaq; Sawaira Sana; Abdul Haseeb Ahmed; Abdullah M.  Harris

doi:10.1109/ISSOC.2010.5625543

Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm

Zulfiqar Ali^*, Ali Arshad, Umair Razzaq, Sawaira Sana, Abdul Haseeb Ahmed, Abdullah M. Harris

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

6 Citations (Scopus)

Abstract

A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.

Original language	English
Title of host publication	2010 International Symposium on System-on-Chip Proceedings, SoC 2010
Pages	158-162
Number of pages	5
DOIs	https://doi.org/10.1109/ISSOC.2010.5625543
Publication status	Published - 21 Dec 2010
MoE publication type	A4 Article in a conference publication
Event	International Symposium on System-on-Chip - Tampere, Finland Duration: 29 Sep 2010 → 30 Sep 2010 Conference number: 12

Conference

Conference	International Symposium on System-on-Chip
Abbreviated title	SoC
Country	Finland
City	Tampere
Period	29/09/2010 → 30/09/2010

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10.1109/ISSOC.2010.5625543

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@inproceedings{36ad8d1938ba486d890042ce0a51c0a7,

title = "Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm",

abstract = "A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.",

author = "Zulfiqar Ali and Ali Arshad and Umair Razzaq and Sawaira Sana and Ahmed, {Abdul Haseeb} and Harris, {Abdullah M.}",

year = "2010",

month = dec,

day = "21",

doi = "10.1109/ISSOC.2010.5625543",

language = "English",

isbn = "9781424482764",

pages = "158--162",

booktitle = "2010 International Symposium on System-on-Chip Proceedings, SoC 2010",

note = "International Symposium on System-on-Chip, SoC ; Conference date: 29-09-2010 Through 30-09-2010",

}

Ali, Z, Arshad, A, Razzaq, U, Sana, S, Ahmed, AH & Harris, AM 2010, Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm. in 2010 International Symposium on System-on-Chip Proceedings, SoC 2010., 5625543, pp. 158-162, International Symposium on System-on-Chip, Tampere, Finland, 29/09/2010. https://doi.org/10.1109/ISSOC.2010.5625543

Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm. / Ali, Zulfiqar; Arshad, Ali; Razzaq, Umair; Sana, Sawaira; Ahmed, Abdul Haseeb; Harris, Abdullah M. .

2010 International Symposium on System-on-Chip Proceedings, SoC 2010. 2010. p. 158-162 5625543.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm

AU - Ali, Zulfiqar

AU - Arshad, Ali

AU - Razzaq, Umair

AU - Sana, Sawaira

AU - Ahmed, Abdul Haseeb

AU - Harris, Abdullah M.

N1 - Conference code: 12

PY - 2010/12/21

Y1 - 2010/12/21

N2 - A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.

AB - A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.

UR - http://www.scopus.com/inward/record.url?scp=78650199062&partnerID=8YFLogxK

U2 - 10.1109/ISSOC.2010.5625543

DO - 10.1109/ISSOC.2010.5625543

M3 - Conference contribution

AN - SCOPUS:78650199062

SN - 9781424482764

SP - 158

EP - 162

BT - 2010 International Symposium on System-on-Chip Proceedings, SoC 2010

T2 - International Symposium on System-on-Chip

Y2 - 29 September 2010 through 30 September 2010

ER -